E&ICT Academy IIT Guwahati Presents
12 Months Online Professional Certification Program on

VLSI & Semiconductor Industry Essentials

An employer-driven professional certification with live mentorship, explicit Hands-on Training, real projects and a portfolio-grade capstone.

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  • ⏱ Duration: 12 Months
  • 💻 Mode: Live + On-demand
  • 🏆 Certificate: Industry Recognized
Book a free live webinar to know more
No payment required to apply. Scholarships available.

About the Course

A premium, compact certification crafted by IIT Guwahati Professor, Research Scholars and Staff. You'll build portfolio-grade deliverables, receive 1:1 mentor feedback and participate in mock interviews curated to fast-track your hiring readiness. Research paper writing under the guidance of IIT Guwahati veterans.

  • Flexible learning — recordings + weekly live sessions.
  • Practical projects — real company briefs, mentor reviews.
  • Career support — portfolio & interview coaching.
  • Research — research paper writing assistance for further studies.
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Duration

7–8 hours weekly engagement through live, query and hands-on sessions. Total 4 semesters of three months each.

Tools

Training on industrial tools like MAGIC, SPICE, Xilinx Vivado, Quartus Prime, Questa Sim, Synopsys, Cadence and many more.

Career Prep

Resume, portfolio, mock interviews and important interview facing tips and tricks.

Community

Active cohort groups with E&ICT Academy IIT Guwahati alumni network.

Activities

On-campus orientation and immersion at the beginning and completion of the program.

Capstone & Research

Showcase-ready project reviewed by mentors and research paper writing guidance from IIT Guwahati veterans.

Key Features

Designed to make you employer-ready and future studies.

Hands-on

Project-based learning with real deliverables.

Mentors

1:1 mentor reviews and query assistance just an email away.

Live Sessions

Weekly interactive sessions and master classes from eminent experts.

Certification

Industry-recognized certificate on completion of every semester.

Eligibility

Open to professionals with 0+ years experience — applicants with demonstrable project work preferred. Need-based scholarships available.

Next cohort:
April, 2026

Learning Path Visualization

Step-by-step path from fundamentals to capstone and research covering 15 detailed Modules.

Foundational Digital Design

Initial 3 Modules of 90 Hours duration forming Semester I of the course.

Semiconductor Fabrication & Device Design

Intermediate 4 Modules of 90 Hours duration forming Semester II of the course.

Hands-on Tool for VLSI

Advanced 3 Modules of 90 Hours duration forming Semester III of the course.

VLSI and Semiconductor Industry Essentials

Portfolio-grade final capstone project, mock interviews and research paper writing.

Syllabus

Detailed module breakdown — expand to view topics and resources.

Logic Gates (AND, OR, NOT etc.), Boolean Algebra, Gate level combinational circuits: Multiplexer/ Demultiplexer, Encoder/ Decoder, Adder/ Subtractor
5h
Comparator, Parity generators, Gate level sequential circuits: latches, Flip-flops (RS, JK, D, T, and Master Slave), Registers
6h
Counters: Ripple and Ring, Shift Register and Counters, Design of synchronous sequential finite state machine, Analysis of synchronous sequential finite state machine
5h
Hands-on: Verification and interpretation of truth table for various gates, Realization of logic functions with the help of universal gates, Boolean functions using MUX, Design of MUX and DEMUX using Universal logic Gates, decoder/de-multiplexer and encoder using logic gates, BCD to 7 Segment LED display decoder, Half adder by using basic and universal gates, Half and Full Subtractor, one bit and two bit comparator using logic gates, NOR gate latch, JK Flip-Flop, truth table of RS, JK, T and D flip-flops using NAND & NOR gates, two-bit ripple counter, synchronous up down counter.
14h
Key stages in design, verification, Synthesis, Physical Design
5h
MOS Circuits, Sheet resistance and area capacitances of layers, Wiring capacitances, CMOS inverter, CMOS Gates, Delays, Logical and Electrical Efforts,Gate Sizing
7h
Counters: Ripple and Ring, Shift Register and Counters, Design of synchronous sequential finite state machine, Analysis of synchronous sequential finite state machine
5h
Buffering, Asymmetric gate, Skewed gates, Ratioed logic, Switching power dissipation, Stick Diagram
5h
MOSFET scaling, Dynamic CMOS design
4h
Hands-on: Implementation and Testing of NMOS and PMOS characteristics, Inverter characteristics, Flip Flop, Latches, Logic Gates, Counter, Adder, Multiplier and Sequence Detector using MAGIC and SPICE.
9h
Introduction to digital circuit design flow, Verilog Language introduction, Levels of abstraction, Module, Ports types and declarations, Registers and nets, Arrays, Identifiers, Parameters
5h
Relational, Arithmetic, Logical, Bit-wise shift Operators, Writing expressions, Behavioral Modeling, Structural Coding, Continuous Assignments, Procedural Statements, Always, Initial Blocks, begin end, fork join
8h
Blocking and Non-blocking statements, Operation Control Statements, If, case, Loops: while, for-loop, forever, repeat, Combination and sequential circuit designs, Memory modeling, state machines, CMOS gate modeling, Writing Tasks, Writing Functions
8h
Compiler directives, Conditional Compilation, System Tasks, Gate level primitives, User defined primitives, Delays, Specify block, Testbenchs, modeling, timing checks, Assertion based verification, Code for synthesis, Advanced topics, Writing reusable code
9h
Hands-on: Practice coding small projects like adders, multiplexers, and simple controllers during the practical sessions. Implementation of combinational circuits and sequential circuits using Verilog/VHDL. Tools Required: Xilinx Vivado, Quartus Prime
Functional Verification overview, System Verilog Course overview, Operators, Data types (Int, Void, String, Userdefined, Enumeration, class), Arrays (Fixed Size Array, packed array, unpacked array, Dynamic array, Associate Array, Queues), Procedural Statements and Flow Control (foreach, repeat forever, break and continue, event control, Named block), Object Oriented Programming Overview, Advanced Data types, Fork join, Inter process synchronization, Project to learn all SV language constructs
12h
Program, Scheduling semantics, Task, Function, Constraints, Randomization, Functional and code coverage, Assertions and Assertion based verification, Direct Programming Interface (DPI), Configuration libraries, Packages, XMR, Test bench Architecture
13h
Hands-on Tools: Questa Sim, Modelsim, NCSIM, VCS.
UVM Methodology, How UVM evolved?, UVM class library, UVM Class Library, Macros, Utilities, UVM TB Architecture, Command line processor, Reporting classes, Objections, UVM Factory
12h
Configuration DB, Resource DB, TLM1.0, Simulation Phases, Sequences, Sequencers, Test case development, Configuring TB Environment, Different testbench component coding, Different styles of sequence development, Sequence library, Virtual Sequencer, Virtual sequences
13h
Hands-on Tools: Questa Sim, Modelsim, NCSIM, VCS.
Linux Commands – Hands On, Vim Editor – Hands On
4h
TCL Programming Basics, Data Manipulation, File Handling
10h
Python: Programming Basics, Data Manipulation, File Handling, Basic Statistics, Data Visualization
11h
Hands-on Tools: Unix/Linux Environment, TCL Utility, Python Utility
Clock Domain Crossing (CDC): Fundamentals of CDC, Metastability issues in CDC, Types of CDC signals: Single-bit control signals, Multi-bit data signals, Handshake-based transfers, CDC design techniques: 2-flop synchronizer, Pulse synchronizer, Handshake synchronizer, FIFO-based synchronizer, Timing constraints and STA considerations for CDC, CDC verification techniques: Simulation limitations, Formal verification methods, Static CDC tools
5h
Reset Domain Crossing (RDC): Fundamentals of RDC, Asynchronous vs synchronous resets, Metastability due to reset deassertion, Reset release synchronization methods, Safe reset design practices, Reset tree design in large SoCs, RDC verification and sign-off checks
5h
Synchronizers: Basics of metastability, Synchronizer design principles, Common synchronizer architectures, 2-flop synchronizer, Multi-flop synchronizer, Muller C-element synchronizer, Gray code synchronizer, MTBF (Mean Time Between Failure) calculation, Impact of technology scaling on synchronizers, Best practices for synchronizer placement and physical design, Case studies in synchronizer failures
5h
Hands-on Tools: QuestaSim, VCS, or Xcelium
Introduction, Logical Vs Physical, Timing Models, Inputs required in Details, Steps in Synthesis: Analyse/Elaborate, Importing Constraints, Importing DEF & UPF (optional), Compile, Optimization, Scan (DFT) Insertion, Compile incremental, Debuging/Resolving the Errors, Important Commands, Qualifying netlist, Generating outputs.
Hands-on Tools: Synopsys DC, FC Or Cadence Genus OR YoSys
7h
Logical Equivalence Check: Introduction, Need for LEC, Modes, Debuging & Resolving the mismatches in netlists, Need for testing, DFT Basics, SoC Scan architecture overview, Types of Scan, ATPG DRC Debug, ATPG Simulation Mismatch Debug, DFT Diagnosis, JTAG.
Hands-on Tools: Synopsys FV Or Cadence CLP
10h
MemoryBIST, LogicBIST, Scan and ATPG, Test compression technigues, Hierarchical Scan Design, DFT Compiler: Overview, Flows Supported by DFT Compiler, Scan Insertion Flow, DFT Compiler Flow and supported Commands, Tetramax/Tessent Flow for ATPG, Steps involved in ATPG mode, ATPG models targeted by Tetramax/Tessent.
Hands-on Tools: Tetramax/ Tessent
13h
Floor planning: Inputs of Floorplan, Sanity Checks, Macro Placement Guidelines, Qualifying the Floorplan, Power Planning, Placement: Standard cell placement, Global routing, Congestion analysis, Timing analysis, Qualifying the placement db.
20h
Clock Tree Synthesis: Specification file, NDR rules, Clock tree build and Balance, CCD Concurrent Clock and Data Optimization, Clock tree optimization, Crosstalk, Timing Analysis, Routing and Optimization: Overview & goals, Constraints, Pre-route checks, Related terminologies, Types of routing and Optimization, Challenges in routing (DRC/LVS), Timing Analysis, ECO (Engineering Change Order), GDS-II Generation.
20h
Hands-on Tools: Synopsys ICC, FC Or Cadence Innovus OR OpenRoad Tools.
Basic Static Timing Analysis Concept, Input to STA tool, Setup Time, Hold Time, Slack, Clock Latencies + Clock Skew, Library Overview, Recovery and Removal Time, Propagation Delay Calculations, Timing Paths, Timing Exception, Asynchronous Path, Clock Gating
10h
STA VS DTA, Generated Clock, Virtual Clock, Unateness + Functionality, Uncertainity, Jitter, Design Constraints in details: Timing Constraints, Design Rule Constraints, Exceptions, Area Constraints, System Interface constraints, Multi-voltage and power optimization Constraints, Advance STA Concept: Onchip Variation (OCV), Advance Onchip variation (AOCV), Parametric On chip variation (POCV), Signal Integrity Effects
10h
Hands-on Tools: OpenSTA/ PrimeTime/ Tempus
Module 401 Capstone Project: The program culminates in a capstone project where you apply all the concepts learned. This project, which could be a simple processor, a memory controller, or a communication protocol block, provides invaluable hands-on experience with industry-standard EDA (Electronic Design Automation) tools. The project should cover both the design and verification stages.
30h
Module 402 Final Project Presentation: The final project presentation will be based on the capstone project developed by the participants.
5h
Module 403 Research Methodology & Research Writing: The research paper writing will be based on the Capstone project made by the participants.
35h
Module 404 and 405: Career Counselling and Interview Facing Tips & Tricks
20h

Course Mentors

Experienced practitioners from IIT Guwahati in this field.

Prof. Gaurav Trivedi
Prof. Gaurav Trivedi
Professor, EEE, IIT Guwahati

Research Areas: Circuit Simulation (Analog, RF & Digital) and VLSI CAD, Electronics System Design, Computer Architecture, Semiconductor Devices, Hardware Security, Embedded Systems and IoT, High Performance Computing, Large Scale Optimization and Machine Learning.

Prof. Shaik Rafi Ahamed
Prof. Shaik Rafi Ahamed
Professor, EEE, IIT Guwahati

Key Research Areas: VLSI Architectures for Signal Processing, Machine Learning and Communication Algorithms, Digital IC Design, Adaptive Signal Processing and Biomedical Signal Processing.

Dr. Mahima Arrawatia
Dr. Mahima Arrawatia
Assistant Professor, EEE, IIT Guwahati

Research Areas: Energy Harvesting, RF Circuit Design, Microstrip Antennas.

Meet the Instructors

Instructors of this course are IIT Guwahati Research Scholars and Staff in this field.

Dr. Sushree Sila P. Goswami
Dr. Sushree Sila P. Goswami
Project Manager, Daksh Gurukul

Key Research Areas: Hardware security, Digital VLSI system design, High Performance Computing, Low-power architecture design.

Dr. Amol K. Boke
Dr. Amol K. Boke
Principal Scientist, NiNELabs, IIT Guwahati

Key Research Areas: Hardware Architecture, VLSI Design, Signal Processing.

Dr. Naorem Yaipharenba Meitei
Dr. Naorem Yaipharenba Meitei
Sr. Project Engineer, NiNELabs, IIT Guwahati

Key Research Areas: Processor, Co-processor Design & Architecture development, RTL Design, FPGA Implementation, VLSI EDA.

Dr. Vikash Prasad
Dr. Vikash Prasad
Sr. Project Engineer, NiNELabs, IIT Guwahati

Key Research Areas: Analog and Mixed Signal Design

Mrs. Aditi Biswas Das
Mrs. Aditi Biswas Das
Project Engineer, E&ICT Academy, IIT Guwahati

Key Research Areas: Analog VLSI Design, Mixed Signal VLSI Design, 6G Communications, IoT and Embedded Systems, Emerging AI for enhancing productivity.

Get in touch

Questions about the course or eligibility? Drop us a message and we'll respond within 48 hours.

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